The present invention relates to semiconductor integrated circuit devices.
Regarding an IC wherein a bipolar element executing and analog operation and complementary MOS elementexecuting digital operations are formed on a single semiconductor substrate, so the analog and digital devices coexist (hereinbelow, termed the "Bi-CMOS.IC"), a structure employing Al (aluminum) for the gate of the MOS element has heretofore been well known as disclosed in, for example, the official gazette of Japanese Laid-open Patent Application No. 56-152258. In case of manufacturing the Bi-CMOS.IC of the Al gate structure, it is common practice to adopt a method in which an N.sup.- -type Si layer epitaxially grown on a p.sup.- -type Si (silicon) substrate is isolated into several island regions of Si by p-n junctions formed by p-type diffusion, whereupon the bipolar element and the CMOS elements are formed in the respective island regions of the n.sup.- -type Si layer. However, the Al gate has a width of about 8 .mu.m and cannot be made less, and the are of the isolation region (isolation portion) cannot be reduced with the p-n junction isolation. Therefore, the prior art has had a problem in point of a high density of integration.
According to the official gazette which discloses a process for manufacturing the Bi-CMOS.IC of the Al gate structure an isolation region, the base (p-type) region of a bipolar element and a p-type well for forming an n-channel MOS element are simultaneously formed by diffusion. Further, according to the official gazette, p.sup.+ -type diffusions for the contact portion of the base, the source and drain of a p-channel MOS element and the surface part of the isolation region are used in common, while n.sup.+ -type diffusions for the emitter of the bipolar element and the source and drain of the n-channel MOS element are used in common. With such process, bipolar characteristics are inferior because the impurity concentration of the base is as low as that of the p-type well. There are, for example, the problems that the f.sub.T (current-gain-bandwidth frequency) is low (40 MHz), that the output impedance is low and that a high injection effect is liable to occur. Moreover, a high density of integration cannot be much expected because of the Al gate structure.
A Bi-MOS IC of Si gate structure which can achieve a higher density of integration than the Al gate structure has been known from the official gazetter of Japanese Laid-open Patent Application No. 55-157257, and Bi-CMOS ICs of Si gate structure have been known from the official gazettes of Japanese Laid-open Patent Applications Nos. 56-7462 and 56-15068. Since the Bi-MOS IC or the Bi-CMOS IC disclosed in the official gazette has the inter-element isolation structure which employs the LOCOS (Local Oxidation of Silicon) technique, it can achieve a still higher density of integration. However, in case of the IC's disclosed in the official gazettes of Nos. 55-157257 and 56-15068, substrate potentials are restricted, and parasitic thyristors are prone to develop. On the other hand, in case of the IC disclosed in the official gazette of No. 56-7462, circuit design is restricted because a substrate is used as the collector region of a bipolar element.